1. Technical Field
The present disclosure relates to an improved static random-access memory (SRAM) memory device and to a method for testing the same.
2. Description of the Related Art
As shown in FIG. 1, an SRAM memory device 1 of the known type is formed by a memory array 2 including a plurality of SRAM cells 3, these latter being arranged so as to define a first number N of rows and a second number M of columns.
In addition, the SRAM memory device 1 comprises a row decoder 4, a first pre-charge circuit 6 and a read/write circuit 8. Furthermore, the SRAM memory device 1 comprises a number of first conductive paths WL equal to the number N of rows, these first conductive paths WL being known as word lines and being connected to the row decoder 4; each word line WL is further connected to the SRAM cells 3 of the corresponding row of the memory array 2.
The SRAM memory device 1 includes also, for each column of SRAM cells 3, a first and a second bit-line BLC, BLT. In particular, given a column of SRAM cells 3, the corresponding first and second bit-line BLC, BLT are both connected to the first pre-charge circuit 6 and to the read/write circuit 8 (these latter connections not being shown), as well as to the SRAM cells 3 of the corresponding column of the memory array 2. Although not shown in FIG. 1, the SRAM memory device may also include a multiplexing circuit, which allows the device to write several words in each row; however, for the sake of simplicity, in the following it will be assumed that such a multiplexing circuit is absent.
In greater detail, as shown in FIG. 2, each SRAM cell 3 is formed by a first and a second transistor PUF, PUT, generally of the P-MOS type and referred to as the first and the second load transistor, and a third and a fourth transistor PDF and PDT, generally of the N-MOS type and referred to as the first and the second pull-down transistor. Furthermore, each SRAM cell 3 comprises a fifth and a sixth transistor PGF and PGT, generally of the N-MOS type and referred to as the first and the second selecting transistor.
The control terminal of the first load transistor PUF is connected to the control terminal of the first pull-down transistor PDF, thereby defining a first node T. A first conductive terminal of the first load transistor PUF is connected to a first conductive terminal of the first pull-down transistor PDF, thereby defining a second node F. A second conductive terminal of the first load transistor PUF is connected to a third node DD, which, in use, is set to a supply voltage VDD; a second conductive terminal of the first pull-down transistor PDF is connected to ground.
The control terminal of the second load transistor PUT and the control terminal of the second pull-down transistor PDT are both connected to the second node F. A first conductive terminal of the second load transistor PUT and a first conductive terminal of the second pull-down transistor PDT are both connected to the first node T. Furthermore, a second conductive terminal of the second load transistor PUT is connected to the third node DD, whereas a second conductive terminal of the second pull-down transistor PDT is connected to ground.
In addition, the control terminals of the first and the second selecting transistor PGF, PGT are both connected to the word line WL which corresponds to the considered SRAM cell 3. The first and the second conductive terminal of the first selecting transistor PGF are respectively connected to the second node F and the first bit line BLC of the considered SRAM cell 3; the first and the second conductive terminals of the second selecting transistor PGT are respectively connected to the first node T and the second bit line BLT of the considered SRAM cell 3.
As is known, each SRAM cell 3 stores a logic value (bit), which is equal to “1” or “0”. Each stored logic value corresponds to a pair of voltages of the first and the second node T, F. As an example, when the SRAM cell 3 stores the logic value “1”, the voltage on the first node T is high, whereas the voltage on the second node F is low; conversely, when the SRAM cell 3 stores the logic value “0”, the voltage on the first node T is low, whereas the voltage on the second node F is high. Of course, the relationships between the stored logic values and the voltages on the first and second node T, F may be reversed. However, for the sake of simplicity, in the following it is assumed that the logic value “1” corresponds to a high voltage on the first node T and a low voltage on the second node F.
Operatively, the row decoder 4 may be controlled so as to dynamically select one from among the N word lines WL, namely to set a high voltage on the selected word line WL, and to set a low voltage on all the other word lines WL. To this end, the row decoder 4 receives an address signal ADDR, which represents the word line WL to be selected. In such a way, all the SRAM cells 3 of the row which corresponds to the address signal ADDR are selected, namely the corresponding first and second node T, F are connected to the corresponding second and first bit lines BLT, BLC, thereby allowing the device to read or write the selected SRAM cells 3, as described hereinbelow.
That being said, and referring again to FIG. 1, the SRAM memory device 1 further includes a dummy read cell 20, a dummy row 22, a dummy row decoder 24, a dummy read column 26, a second pre-charge circuit 28 and a dummy amplifier 30. Furthermore, the SRAM memory device 1 includes a controller circuit 40.
In detail, the dummy row 22 comprises a number M of SRAM memory cells 3 (not shown), which are connected to the dummy row decoder 24 by means of a dummy word line DWL; furthermore, each SRAM cell 3 of the dummy row 22 is connected to the corresponding pair of first and second bit line BLC, BLT. In addition, the dummy read cell 20 is formed by a “hard-wired” SRAM cell, namely by an SRAM cell whose first and second node T, F are set to fixed voltages. Put in other words, the dummy read cell 20 stores a fixed logic value; furthermore, the dummy read cell 20 is connected to the dummy word line DWL.
The dummy read column 26 comprises a number N of further SRAM cells (not shown); these further SRAM cells are not active, namely the control terminals of the first and second selecting transistor PGF, PGT of each of these further SRAM cells are connected to ground, so that these further SRAM cells act as a capacitive load. Therefore, the SRAM cells of the dummy read column 26 cannot be accessed.
In greater detail, all the SRAM cells of the dummy read column 26 and the dummy read cell 20 are connected to the same pair of first and second bit line, hereinafter referred to as the first and the second dummy bit line DBLC, DBLT, these first and second dummy bit line DBLC, DBLT being further connected to the second pre-charge circuit 28, as well as to the dummy amplifier 30 (this connection not being shown in FIG. 1). The SRAM cells of the dummy read column 26 define a capacitive load of the first and second dummy bit line DBLC, DBLT.
From a practical point of view, the memory array 2, the dummy row 22, the dummy read cell 20 and the dummy read column 26 form a sort of expanded memory array, which is formed by (N+1)*(M+1) SRAM cells.
Operatively, the controller circuit 40 is adapted to receive, besides the address signal ADDR, an external clock signal clk and a write enable signal WEN. The external clock signal clk represents a clock, namely a periodic squared pulse train.
In detail, based upon the external clock signal clk, the controller circuit 40 may access the memory array 2, either to write or read a selected row of the memory array 2. In greater detail, at each clock pulse of the external clock signal clk, the controller circuit 40 either writes or reads a row of the memory array 2, according to the logic value of the write enable signal WEN; in particular the writing or reading is performed at an address (namely, a row of the memory array 2) indicated by the address signal ADDR.
In particular, in order to avail of a timing signal for carrying out the reading or the writing, the controller circuit 40 generates an internal clock signal clk-int, based upon the external clock signal clk, this internal clock signal clk-int being inputted to both the row decoder 4 and the read/write circuit 8, as well as to the dummy row decoder 24. In addition, based upon the external clock signal clk, the controller circuit 40 generates a pre-charge signal pch, which is inputted to both the first and the second pre-charge circuit 6, 28. In particular, the pre-charge signal pch is active when low, namely the first and second pre-charge circuit 6, 28 are activated when the pre-charge signal pch is low. Therefore, referring as an example to the second pre-charge circuit 26, when the pre-charge signal pch is low, both the first and the second dummy bit line DBLC, DBLT are driven by the second pre-charge circuit 26 to a voltage equal to the supply voltage VDD.
In greater detail, as shown in FIG. 3, each rising edge of the internal clock signal clk-int is triggered by a corresponding rising edge of the external clock signal clk, from which it is delayed by a certain amount of time, which depends on the controller circuit 40. The same applies for the rising edges of the pre-charge signal pch, whose rising edges are triggered by the rising edges of the external clock signal clk.
Furthermore, after each rising edge of the internal clock signal clk-int, both the dummy word line DWL and the word line WL corresponding to the row indicated by the address signal ADDR (hereinafter referred to as array word line WLi) are asserted, namely are set at a high voltage, respectively by the dummy row decoder 24 and the row decoder 4. In addition, the corresponding rising edge of the pre-charge signal pch causes the first and the second pre-charge circuit 6, 28 to stop the pre-charge on all of the first and second bit lines BLC, BLT, as well as on the first and second dummy bit line DBLC, DBLT.
From a practical point of view, each rising edge of the internal clock clk-int causes an inhibition of the pre-charge, as well as the assertion of the dummy word line DWL and of one among the word lines WL, in particular the array word line WLi. Put in other words, if reference is made to the signals sDWL and sWLi to indicate the electric signals on the dummy word line DWL and the array word line WLi, each rising edge of the internal clock signal clk-int causes a corresponding rising edge of each of the signals sDWL and sWLi.
Afterwards, according to the write enable signal WEN, a reading or writing is performed. In both cases, a discharge occurs on one of the first and second dummy bit lines DBLC, DBLT, depending on the fixed voltages of the first and second node T, F of the dummy read cell 20. This discharge is detected and performed by the dummy amplifier 30, which acts as a dummy write discharge circuit, and which generates a timing signal RESET. In particular, upon detecting such a discharge, the dummy amplifier 30 generates a falling edge of the timing signal RESET, delayed with respect to the rising edge of the internal clock signal clk-int. The timing signal RESET is inputted to the read/write circuit 8.
Furthermore, based on the write enable signal WEN, during the time interval between the rising edge of the pre-charge signal pch and the falling edge of the timing signal RESET, the read/write circuit 8 performs one of the following two sets of operations.
In detail, in case the write enable signal WEN indicates writing, the read/write circuit 8 writes the SRAM cells 3 of the array word line WLi. To this end, as soon as the pre-charge signal pch goes high, each of the first and second bit line BLC, BLT of each of the SRAM cells of the array word line WLi is driven by the read/write circuit 8 to a corresponding voltage; to this end, the read/write circuit 8 comprises a plurality of writing driving circuits (not shown). In such a way, when the array word line WLi is asserted, given an SRAM cell of the array word line WLi, the voltages on the corresponding first an second node T, F are forced by the voltages on the corresponding second and first bit line BLT, BLC, thereby causing the given SRAM cell to store a given logic value.
On the other hand, if the write enable signal WEN indicates reading, the read/write circuit 8 reads the SRAM cells 3 of the array word line WLi. In detail, the end of the pre-charge and the assertion of the array word line WLi causes, a considered SRAM cell among the SRAM cells connected to the array word line WLi, the discharge of one of the corresponding first and second bit line BLC, BLT, depending on the logic value stored within the considered SRAM cell. From a practical point of view, this discharge causes a voltage difference between the first and second bit line BLC, BLT connected to the considered SRAM cell; such a voltage difference is detected by the read/write circuit 8 (to this end, the read/write circuit 8 comprises a plurality of reading driving circuits), thereby allowing the device to detect the logic value stored in the considered SRAM cell. In particular, the reading driving circuits are controlled by the timing signal RESET and each of them detects the respective voltage difference at the falling edge of the timing signal RESET.
In greater detail, the timing signal RESET is inputted also to the controller circuit 40, which generates a corresponding falling edge of the internal clock signal clk-int, as well as a corresponding falling edge of the pre-charge signal pch. In addition, both the dummy word line DWL and the array word line WLi are driven to a low voltage, so as to be ready to receive a new address signal ADDR and perform a new reading or writing at the next rising edge of the external clock signal clk.
When the pre-charge signal pch goes down, the first and the second pre-charge circuit 6, 28 start again to pre-charge the bit lines to which they are connected. In particular, the new pre-charge of the first and second dummy bit line DBLC, DBLT is detected by the dummy amplifier 30, which generates a rising edge of the timing signal RESET.
From a practical point of view, the dummy row 22, the dummy read cell 20 and the dummy column 26 represent a dummy path, also known as self-timing path, which can be used to determine the time performances of the SRAM memory device 1, and in particular to determine the discharge time of the first and second bit lines BLC, BLT. To this regard, it has to be noted that the dummy path is designed so that, when the first (or second, as the case may be) dummy bit line DBLC is discharged, it may be safely assumed that also the bit lines of the memory array 2 which have to be discharged (depending on the stored logic values) have already been discharged. Therefore, the falling edge of the timing signal RESET defines a time instant at which the reading or writing has indeed been accomplished.
Put in other words, the discharge time of the dummy read cell 20 (i.e., of one of the first and second dummy bit lines DBLC, DBLT) defines an internal limit to the speed of the SRAM memory device 1.
That being said, known SRAM cells are affected by the so-called write time problem. In general, the write time is the time taken by the SRAM cell to flip the voltages of its first and second node F, T following a voltage change on the first and second bit line BLC, BLT; such a voltage change being forced during a writing operation.
In detail, consider the second node F, and assume that the voltage VF on the second node F is low. In such a case, the first load transistor PUF is “weak”, namely is resistive, and a relatively long time is required to pull up the voltage VF to a high level, such as during a writing operation aiming at setting the voltages VF and VT to, respectively, a high and a low voltage. Similar problems arise on the first node T. In this case, the second load transistor PUT is weak, thereby leading to long writing times, namely to writing times longer than the designed writing times.
Long write times may cause problems, in particular at high frequencies, namely at frequencies such that the time window available for carrying out a writing/reading is so small that even a small weakness of the SRAM cells can cause errors.
In detail, long write times may lead to two different kinds of failures. In greater detail, a so-called read failure may occur, in case the voltage difference between the first and second node T, F is such that the read/write circuit 8, during a reading which follows the abovementioned writing operation, does not detect the correct logic value. In fact, as already said, the voltage VF is less than designed for such a situation, and, since the second node F controls the second pull-down transistor PDT, the voltage VT is higher than designed, thereby leading to an incorrect detection by the read/write circuit 8, and in particular by the reading driving circuits contained therein.
Furthermore, long write times may lead to the so-called static noise margin (SNM) failure. With reference to the above example, it may happen that an insufficient voltage VF causes a SNM failure during the reading operation. In fact, a relatively low voltage VF causes a low conductivity of the second pull-down transistor PDT, thereby leading to a voltage increase on the first node T. Such a voltage increase on the first node T may cause a flip of the logic value stored by the SRAM cell, namely an undesired switching of the SRAM cell.
Unfortunately, failures due to the write time problem cannot be easily detected by means of traditional testing methods. In fact, high speed access is used to detect write time induced failures, therefore a dedicated test chip is used; such a test chip being provided with an embedded built-in self test (BIST) circuit; such a BIST circuit is in turn optimized to perform high speed accesses. This kind of test chip is expensive and limited to specific sizes of the SRAM memory device to be tested.